Modern memory devices are available in numerous configurations with different operating specifications. For example, dynamic, static and non-volatile memories are available in multiple architectures and can be operated in different modes. Those skilled in the art will recognize page mode, synchronous, burst, pipe line, and bus efficient (BE) as examples of different data communication operations commercially available.
One type of memory is the static random access memory (SRAM). An SRAM is designed to store data in memory cells formed as a static latch circuit. This type of memory does not require the data refresh operations necessary in a conventional DRAM. The SRAM, however, requires additional integrated die area to fabricate a memory cell.
With the constant development of faster computer and communication applications, the data rates in which a memory circuit must operate continue to increase. To address the need for increased data rates, a variety of memories are produced in a variety of designs which provide different methods of reading from and writing to the memory cells of the memory. Page mode operations are defined by the method of accessing a row of a memory cell array and randomly accessing different columns of the array. Data stored at the row and column intersection can be read and output while that column is accessed. Page mode memories require access steps which limit the communication speed of the memory circuit.
Another type of memory is a burst access memory which receives one address of a memory array on external address lines and automatically addresses a sequence of columns without the need for additional column addresses to be provided on the external address lines. By reducing the external address input signals, burst memory circuits are capable of outputting data at significantly faster communication rates than the above described memory circuits.
Synchronous memory devices, either dynamic or static, operate in synchronization with an externally provided clock signal and can typically function in burst read and write modes to reduce external address input signals. Synchronous burst SRAM devices, known as PB1 and PB2, are also available as pipelined and non-pipelined (flow-through) devices. Inactive data bus times are often experienced when changing the operation of an SRAM from a write operation to a read operation. This "idle" bus time is eliminated in bus efficient (BE) memory devices. These memories receive external addresses one or more clock cycles prior to its corresponding data.
The above described synchronous and BE memories are manufactured and sold as separate devices which require specifically designed integrated circuits. For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a single integrated circuit memory device which can be operated in either synchronous or bus efficient (BE) modes.